{
 "generated": "2026-11-01",
 "node": {
  "id": "org:synopsys",
  "type": "Organization",
  "name": "Synopsys",
  "org_type": "Developer",
  "kind": "company",
  "homepage": "https://www.synopsys.com/",
  "aliases": [
   "新思科技"
  ],
  "entry": "reviewed",
  "by": "landscape-cards",
  "at": "2026-10-29T04:41:11Z",
  "landscape": [
   {
    "map": "chip-design-flow",
    "map_title": "芯片设计全流程",
    "card": "player-synopsys-agentengineer",
    "title": "Synopsys AgentEngineer",
    "layer": "RTL设计 / 前端设计",
    "layer_id": "layer:chip-design-flow--3",
    "role": "primary"
   },
   {
    "map": "chip-design-flow",
    "map_title": "芯片设计全流程",
    "card": "player-synopsys-codeadvisor",
    "title": "Synopsys.ai Copilot · Code Advisor",
    "layer": "RTL设计 / 前端设计",
    "layer_id": "layer:chip-design-flow--3",
    "role": "primary"
   },
   {
    "map": "chip-design-flow",
    "map_title": "芯片设计全流程",
    "card": "player-synopsys-copilot-arch",
    "title": "Synopsys.ai Copilot",
    "layer": "架构设计 与规格定义",
    "layer_id": "layer:chip-design-flow--1",
    "role": "primary"
   },
   {
    "map": "chip-design-flow",
    "map_title": "芯片设计全流程",
    "card": "player-synopsys-dso",
    "title": "Synopsys DSO.ai",
    "layer": "物理设计 / 布局布线",
    "layer_id": "layer:chip-design-flow--6",
    "role": "primary"
   },
   {
    "map": "chip-design-flow",
    "map_title": "芯片设计全流程",
    "card": "player-synopsys-icvalidator",
    "title": "Synopsys IC Validator",
    "layer": "物理验证 DRC/LVS/DFM",
    "layer_id": "layer:chip-design-flow--8",
    "role": "primary"
   },
   {
    "map": "chip-design-flow",
    "map_title": "芯片设计全流程",
    "card": "player-synopsys-mfg-analytics",
    "title": "Synopsys 制造分析",
    "layer": "流片后调试 / 良率分析",
    "layer_id": "layer:chip-design-flow--11",
    "role": "primary"
   },
   {
    "map": "chip-design-flow",
    "map_title": "芯片设计全流程",
    "card": "player-synopsys-primeclosure",
    "title": "Synopsys PrimeClosure / PrimeECO",
    "layer": "时序收敛 / 静态时序分析",
    "layer_id": "layer:chip-design-flow--7",
    "role": "primary"
   },
   {
    "map": "chip-design-flow",
    "map_title": "芯片设计全流程",
    "card": "player-synopsys-primeshield",
    "title": "Synopsys PrimeShield",
    "layer": "时序收敛 / 静态时序分析",
    "layer_id": "layer:chip-design-flow--7",
    "role": "primary"
   },
   {
    "map": "chip-design-flow",
    "map_title": "芯片设计全流程",
    "card": "player-synopsys-rtlarchitect",
    "title": "Synopsys RTL Architect",
    "layer": "架构设计 与规格定义",
    "layer_id": "layer:chip-design-flow--1",
    "role": "primary"
   },
   {
    "map": "chip-design-flow",
    "map_title": "芯片设计全流程",
    "card": "player-synopsys-tso",
    "title": "Synopsys TSO.ai",
    "layer": "DFT / 测试",
    "layer_id": "layer:chip-design-flow--9",
    "role": "primary"
   },
   {
    "map": "chip-design-flow",
    "map_title": "芯片设计全流程",
    "card": "player-synopsys-vso",
    "title": "Synopsys VSO.ai",
    "layer": "功能验证 与仿真",
    "layer_id": "layer:chip-design-flow--4",
    "role": "primary"
   }
  ],
  "landscape_maps": [
   "chip-design-flow"
  ],
  "landscape_n": 11,
  "degree": 0,
  "n_apps": 0,
  "n_models": 0
 },
 "page": "https://xiaopingfeng.com/graph/e/org/synopsys/",
 "out": [
  {
   "type": "placed_in",
   "sentence": "Synopsys出现在 Landscape 的「架构设计与规格定义」",
   "direction": "out",
   "id": "layer:chip-design-flow--1",
   "name": "架构设计与规格定义",
   "reported": false,
   "status": "derived",
   "evidence": [
    {
     "kind": "own",
     "label": "本站页面",
     "text": "Landscape「芯片设计全流程」第 01 层「架构设计与规格定义」：卡片「Synopsys RTL Architect」",
     "url": "https://xiaopingfeng.com/landscape/chip-design-flow/#player-synopsys-rtlarchitect"
    },
    {
     "kind": "own",
     "label": "本站页面",
     "text": "Landscape「芯片设计全流程」第 01 层「架构设计与规格定义」：卡片「Synopsys.ai Copilot」",
     "url": "https://xiaopingfeng.com/landscape/chip-design-flow/#player-synopsys-copilot-arch"
    }
   ]
  },
  {
   "type": "placed_in",
   "sentence": "Synopsys出现在 Landscape 的「RTL设计 / 前端设计」",
   "direction": "out",
   "id": "layer:chip-design-flow--3",
   "name": "RTL设计 / 前端设计",
   "reported": false,
   "status": "derived",
   "evidence": [
    {
     "kind": "own",
     "label": "本站页面",
     "text": "Landscape「芯片设计全流程」第 03 层「RTL设计 / 前端设计」：卡片「Synopsys.ai Copilot · Code Advisor」",
     "url": "https://xiaopingfeng.com/landscape/chip-design-flow/#player-synopsys-codeadvisor"
    },
    {
     "kind": "own",
     "label": "本站页面",
     "text": "Landscape「芯片设计全流程」第 03 层「RTL设计 / 前端设计」：卡片「Synopsys AgentEngineer」",
     "url": "https://xiaopingfeng.com/landscape/chip-design-flow/#player-synopsys-agentengineer"
    }
   ]
  },
  {
   "type": "placed_in",
   "sentence": "Synopsys出现在 Landscape 的「功能验证与仿真」",
   "direction": "out",
   "id": "layer:chip-design-flow--4",
   "name": "功能验证与仿真",
   "reported": false,
   "status": "derived",
   "evidence": [
    {
     "kind": "own",
     "label": "本站页面",
     "text": "Landscape「芯片设计全流程」第 04 层「功能验证与仿真」：卡片「Synopsys VSO.ai」",
     "url": "https://xiaopingfeng.com/landscape/chip-design-flow/#player-synopsys-vso"
    }
   ]
  },
  {
   "type": "placed_in",
   "sentence": "Synopsys出现在 Landscape 的「物理设计 / 布局布线」",
   "direction": "out",
   "id": "layer:chip-design-flow--6",
   "name": "物理设计 / 布局布线",
   "reported": false,
   "status": "derived",
   "evidence": [
    {
     "kind": "own",
     "label": "本站页面",
     "text": "Landscape「芯片设计全流程」第 06 层「物理设计 / 布局布线」：卡片「Synopsys DSO.ai」",
     "url": "https://xiaopingfeng.com/landscape/chip-design-flow/#player-synopsys-dso"
    }
   ]
  },
  {
   "type": "placed_in",
   "sentence": "Synopsys出现在 Landscape 的「时序收敛 / 静态时序分析」",
   "direction": "out",
   "id": "layer:chip-design-flow--7",
   "name": "时序收敛 / 静态时序分析",
   "reported": false,
   "status": "derived",
   "evidence": [
    {
     "kind": "own",
     "label": "本站页面",
     "text": "Landscape「芯片设计全流程」第 07 层「时序收敛 / 静态时序分析」：卡片「Synopsys PrimeShield」",
     "url": "https://xiaopingfeng.com/landscape/chip-design-flow/#player-synopsys-primeshield"
    },
    {
     "kind": "own",
     "label": "本站页面",
     "text": "Landscape「芯片设计全流程」第 07 层「时序收敛 / 静态时序分析」：卡片「Synopsys PrimeClosure / PrimeECO」",
     "url": "https://xiaopingfeng.com/landscape/chip-design-flow/#player-synopsys-primeclosure"
    }
   ]
  },
  {
   "type": "placed_in",
   "sentence": "Synopsys出现在 Landscape 的「物理验证 DRC/LVS/DFM」",
   "direction": "out",
   "id": "layer:chip-design-flow--8",
   "name": "物理验证 DRC/LVS/DFM",
   "reported": false,
   "status": "derived",
   "evidence": [
    {
     "kind": "own",
     "label": "本站页面",
     "text": "Landscape「芯片设计全流程」第 08 层「物理验证 DRC/LVS/DFM」：卡片「Synopsys IC Validator」",
     "url": "https://xiaopingfeng.com/landscape/chip-design-flow/#player-synopsys-icvalidator"
    }
   ]
  },
  {
   "type": "placed_in",
   "sentence": "Synopsys出现在 Landscape 的「DFT / 测试」",
   "direction": "out",
   "id": "layer:chip-design-flow--9",
   "name": "DFT / 测试",
   "reported": false,
   "status": "derived",
   "evidence": [
    {
     "kind": "own",
     "label": "本站页面",
     "text": "Landscape「芯片设计全流程」第 09 层「DFT / 测试」：卡片「Synopsys TSO.ai」",
     "url": "https://xiaopingfeng.com/landscape/chip-design-flow/#player-synopsys-tso"
    }
   ]
  },
  {
   "type": "placed_in",
   "sentence": "Synopsys出现在 Landscape 的「流片后调试 / 良率分析」",
   "direction": "out",
   "id": "layer:chip-design-flow--11",
   "name": "流片后调试 / 良率分析",
   "reported": false,
   "status": "derived",
   "evidence": [
    {
     "kind": "own",
     "label": "本站页面",
     "text": "Landscape「芯片设计全流程」第 11 层「流片后调试 / 良率分析」：卡片「Synopsys 制造分析」",
     "url": "https://xiaopingfeng.com/landscape/chip-design-flow/#player-synopsys-mfg-analytics"
    }
   ]
  }
 ],
 "in": []
}