{
 "generated": "2026-11-01",
 "node": {
  "id": "org:cadence",
  "type": "Organization",
  "name": "Cadence",
  "org_type": "Developer",
  "kind": "company",
  "homepage": "https://www.cadence.com/",
  "aliases": [
   "Cadence Design Systems",
   "楷登电子"
  ],
  "entry": "reviewed",
  "by": "landscape-cards",
  "at": "2026-10-29T04:41:11Z",
  "landscape": [
   {
    "map": "chip-design-flow",
    "map_title": "芯片设计全流程",
    "card": "player-cadence-cerebrus",
    "title": "Cadence Cerebrus(含AI Studio)",
    "layer": "物理设计 / 布局布线",
    "layer_id": "layer:chip-design-flow--6",
    "role": "primary"
   },
   {
    "map": "chip-design-flow",
    "map_title": "芯片设计全流程",
    "card": "player-cadence-chipstack",
    "title": "Cadence ChipStack AI Super Agent",
    "layer": "RTL设计 / 前端设计",
    "layer_id": "layer:chip-design-flow--3",
    "role": "primary"
   },
   {
    "map": "chip-design-flow",
    "map_title": "芯片设计全流程",
    "card": "player-cadence-joules",
    "title": "Cadence Joules RTL Design Studio",
    "layer": "架构设计 与规格定义",
    "layer_id": "layer:chip-design-flow--1",
    "role": "primary"
   },
   {
    "map": "chip-design-flow",
    "map_title": "芯片设计全流程",
    "card": "player-cadence-tempus",
    "title": "Cadence Tempus + ECO",
    "layer": "时序收敛 / 静态时序分析",
    "layer_id": "layer:chip-design-flow--7",
    "role": "primary"
   },
   {
    "map": "chip-design-flow",
    "map_title": "芯片设计全流程",
    "card": "player-cadence-verisium",
    "title": "Cadence Verisium",
    "layer": "功能验证 与仿真",
    "layer_id": "layer:chip-design-flow--4",
    "role": "primary"
   },
   {
    "map": "chip-design-flow",
    "map_title": "芯片设计全流程",
    "card": "player-cadence-verisium-postsilicon",
    "title": "Cadence Verisium(跨阶段复用)",
    "layer": "流片后调试 / 良率分析",
    "layer_id": "layer:chip-design-flow--11",
    "role": "primary"
   }
  ],
  "landscape_maps": [
   "chip-design-flow"
  ],
  "landscape_n": 6,
  "degree": 0.0011,
  "n_apps": 0,
  "n_models": 0
 },
 "page": "https://xiaopingfeng.com/graph/e/org/cadence/",
 "out": [
  {
   "type": "acquired",
   "sentence": "Cadence收购ChipStack",
   "direction": "out",
   "id": "org:chipstack",
   "name": "ChipStack",
   "since": "2025-11",
   "note": "2025-11-11 宣布收购（团队约 20 人并入 Cadence）；EE Times 称同月完成",
   "status": "agent",
   "evidence": [
    {
     "kind": "media",
     "label": "媒体报道",
     "text": "GeekWire 2025-11-11：Cadence 宣布收购 ChipStack",
     "url": "https://www.geekwire.com/2025/cadence-to-acquire-seattle-startup-chipstack-to-boost-chip-design-automation/"
    },
    {
     "kind": "own",
     "label": "本站页面",
     "text": "本站 Landscape「芯片设计全流程」卡片「Cadence ChipStack AI Super Agent」：已从\"公告阶段\"跨过具名客户验证门槛",
     "url": "https://xiaopingfeng.com/landscape/chip-design-flow/#player-cadence-chipstack"
    }
   ]
  },
  {
   "type": "placed_in",
   "sentence": "Cadence出现在 Landscape 的「架构设计与规格定义」",
   "direction": "out",
   "id": "layer:chip-design-flow--1",
   "name": "架构设计与规格定义",
   "reported": false,
   "status": "derived",
   "evidence": [
    {
     "kind": "own",
     "label": "本站页面",
     "text": "Landscape「芯片设计全流程」第 01 层「架构设计与规格定义」：卡片「Cadence Joules RTL Design Studio」",
     "url": "https://xiaopingfeng.com/landscape/chip-design-flow/#player-cadence-joules"
    }
   ]
  },
  {
   "type": "placed_in",
   "sentence": "Cadence出现在 Landscape 的「RTL设计 / 前端设计」",
   "direction": "out",
   "id": "layer:chip-design-flow--3",
   "name": "RTL设计 / 前端设计",
   "reported": false,
   "status": "derived",
   "evidence": [
    {
     "kind": "own",
     "label": "本站页面",
     "text": "Landscape「芯片设计全流程」第 03 层「RTL设计 / 前端设计」：卡片「Cadence ChipStack AI Super Agent」",
     "url": "https://xiaopingfeng.com/landscape/chip-design-flow/#player-cadence-chipstack"
    }
   ]
  },
  {
   "type": "placed_in",
   "sentence": "Cadence出现在 Landscape 的「功能验证与仿真」",
   "direction": "out",
   "id": "layer:chip-design-flow--4",
   "name": "功能验证与仿真",
   "reported": false,
   "status": "derived",
   "evidence": [
    {
     "kind": "own",
     "label": "本站页面",
     "text": "Landscape「芯片设计全流程」第 04 层「功能验证与仿真」：卡片「Cadence Verisium」",
     "url": "https://xiaopingfeng.com/landscape/chip-design-flow/#player-cadence-verisium"
    }
   ]
  },
  {
   "type": "placed_in",
   "sentence": "Cadence出现在 Landscape 的「物理设计 / 布局布线」",
   "direction": "out",
   "id": "layer:chip-design-flow--6",
   "name": "物理设计 / 布局布线",
   "reported": false,
   "status": "derived",
   "evidence": [
    {
     "kind": "own",
     "label": "本站页面",
     "text": "Landscape「芯片设计全流程」第 06 层「物理设计 / 布局布线」：卡片「Cadence Cerebrus(含AI Studio)」",
     "url": "https://xiaopingfeng.com/landscape/chip-design-flow/#player-cadence-cerebrus"
    }
   ]
  },
  {
   "type": "placed_in",
   "sentence": "Cadence出现在 Landscape 的「时序收敛 / 静态时序分析」",
   "direction": "out",
   "id": "layer:chip-design-flow--7",
   "name": "时序收敛 / 静态时序分析",
   "reported": false,
   "status": "derived",
   "evidence": [
    {
     "kind": "own",
     "label": "本站页面",
     "text": "Landscape「芯片设计全流程」第 07 层「时序收敛 / 静态时序分析」：卡片「Cadence Tempus + ECO」",
     "url": "https://xiaopingfeng.com/landscape/chip-design-flow/#player-cadence-tempus"
    }
   ]
  },
  {
   "type": "placed_in",
   "sentence": "Cadence出现在 Landscape 的「流片后调试 / 良率分析」",
   "direction": "out",
   "id": "layer:chip-design-flow--11",
   "name": "流片后调试 / 良率分析",
   "reported": false,
   "status": "derived",
   "evidence": [
    {
     "kind": "own",
     "label": "本站页面",
     "text": "Landscape「芯片设计全流程」第 11 层「流片后调试 / 良率分析」：卡片「Cadence Verisium(跨阶段复用)」",
     "url": "https://xiaopingfeng.com/landscape/chip-design-flow/#player-cadence-verisium-postsilicon"
    }
   ]
  }
 ],
 "in": []
}